1. Field of the Invention
The present invention generally relates to reference voltage generating circuits and A/D and D/A converters using the same. More particularly, the present invention relates to a reference voltage generating circuit which generates a plurality of linear voltages and A/D and D/A converters using the same.
2. Description of the Background Art
The A/D and D/A converters are provided with a reference voltage generating circuit which generates a plurality of different voltages.
The A/D converters compare analog voltages to be digitized with each of the plurality of analog voltages generated by the reference voltage generating circuit, thereby converting the analog voltages into binary data having a predetermined number of bits.
Conversely, the D/A converters select and output, according to a digital signal to be converted into an analog signal, one of the plurality of analog voltages generated by the reference voltage generating circuit, thereby converting the digital signal into an analog signal.
FIG. 8 is a schematic block diagram showing an A/D converter.
Referring to FIG. 8, the A/D converter comprises a reference voltage generating circuit RVG provided between reference voltage receiving terminals 2 and 3, an encoder ENC, and a comparing portion CMPG provided between reference voltage generating circuit RVG and encoder ENC. Reference voltage receiving terminals 2 and 3 receive constant voltages of different magnitudes.
Reference voltage generating circuit RVG equally divides a difference voltage between voltages received at reference voltage receiving terminals 2 and 3 to output a predetermined number of voltages to output terminals T1 to T(l-1) (l=2, 3, . . .).
Comparing portion CMPG comprises (l-1) comparators CMP. Each of the (l-1) comparators CMP is provided to correspond to one of (l-1) output terminals T1 to T(l-1). Each comparator CMP compares an analog voltage received from a corresponding output terminal of reference voltage generating circuit RVG with an analog voltage input from another analog voltage receiving terminal 1 to output a voltage of "H" or "L" level according to the comparison result. The terminal 1 receives an analog voltage which is to be converted into digital data. Therefore, the output signals of comparing portion CMPG indicate to which voltage range the analog voltage belongs, out of l voltage ranges defined by l-1 output voltages of reference voltage generating circuit RVG.
For example, in a case that voltages output through terminals T1 to T (l-1) of reference voltage generating circuit RVG become higher as the terminal number increases, when an analog voltage received at terminal 1 is higher than a voltage derived from terminal T(l-2), all the comparators CMP provided corresponding to output terminals T1 to T(l-2) outputs the same logical level, which is the inverse of that output from the comparator CMP provided corresponding to output terminal T(l-1). Thus, since the logical level of outputs is switched from a certain comparator, the analog voltage is identified as having a magnitude belonging to any of the l voltage ranges.
In the manner described above, the analog voltage applied to terminal 1 is compared with each of the plurality of voltages output from reference voltage generating circuit RVG so as to be converted into digital data.
Encoder ENC encodes the digital output from comparing portion CMPG into binary data of N bits indicative of magnitude of the analog voltage and outputs the encoded signal to digital signal output terminals Dl to DN.
Subsequently, structures of reference voltage generating circuit RVG and comparators CMP will be described. FIGS. 9 and 10 are circuit diagrams showing the structures of reference voltage generating circuit RVG and comparator CMP, respectively, in the A/D converter disclosed in Japanese Patent Laying-Open No. 61-189022.
Referring to FIG. 9, reference voltage generating circuit RGV comprises a main resistor network MR and a sub-resistor network SR.
Main resistor network MR comprises m (m is arbitrary natural number) resistor networks RGl to RGm connected in series between reference voltage receiving terminals 2 and 3. Each of resistor networks RGl to RGm is comprised of a series connection of n (n is arbitrary natural number) resistors having the same resistance value r. Meanwhile, in the diagram, each of resistor networks RGl to RGm is equivalently shown as a single resistor having a resistance value n.times.r.
Sub-resistor network comprises m resistors Rl to Rm connected in series between reference voltage receiving terminals 2 and 3 and having the same resistance value R.
The (m-1) nodes between resistors Rl to Rm constituting sub-resistor network SR are connected to the (m-1) nodes between resistor networks RGl to RGm constituting main resistor network MR in a one-to-one correspondence. Therefore, a difference voltage between voltages applied to reference voltage receiving terminals 2 and 3 is divided by m resistors Rl to Rm in sub-resistor network SR and applied to main resistor network MR. Each of thus divided voltages is further divided by n resistors rl to rn constituting each of respective resistor networks RGl to RGm in main resistor network MR. As a result, voltages of different levels within a range lower than the voltage applied to reference voltage receiving terminal 2 and higher than the voltage applied to reference voltage receiving terminal 3 are derived from nodes A(1, 1) to A(1, n-1), A(2, 1) to A(2, n-1) . . . , A(m, 1) to A(m, n-1) between resistors rl to rn constituting the respective resistor networks RGl to Rgm and from nodes A(1, n) to A(m-1, n) between resistor networks RGl to Rgm. The relationship between these voltages is linear.
Potentials at the above-mentioned nodes A(1, 1) to A(1, n), . . . , A(m, 1) to A(m, n-1) are derived from output terminals T1 to T(l-1) in FIG. 8 (where l=m.multidot.n).
Referring to FIG. 10, comparator CMP comprises a coupling capacitor 8, an output terminal 7, a parallel connection circuit of a switch SW3 and an inverting amplifier 9 provided between output terminal 7 and coupling capacitor 8, and switches SW1 and SW2 provided between coupling capacitor 8, and analog voltage receiving terminal 1 and a corresponding output terminal Tj (j=1, 2, . . . , m.multidot.n-1) of reference voltage generating circuit RVG in FIG. 8, respectively. Switches SW1 and SW3 are controlled by an externally applied control signal .phi. and switch SW2 is controlled by an inverted signal .phi. of the control signal .phi.. Accordingly, switches SW1 and SW3 and switch SW2 are complementarily turned on/off.
In the following, operation of the comparator will be described.
The control signal .phi. first attains and remains at a logical level "H" corresponding to a logical value "1" for a predetermined period and then switched to a logical level "L" corresponding to a logical value "0". All the switches SW1 to SW3 are put in the ON state by the externally applied control voltage of the "H" level, and in the OFF state by the externally applied control voltage of the "L" level. Therefore, during the period in which control signal .phi. represents the voltage level corresponding to the logical value "1", switches SW1 and SW3 are in the ON state while switch SW2 is in the OFF state. When switch SW3 is turned on, inverting amplifier 9 is short-circuited between input and output so that its input and output potentials are equalized. At this time, the potentials at the input and output terminals of inverting amplifier 9 change to a certain potential Vb (generally about Vdd/2, with Vdd representing drive voltage of inverting amplifier 9) which is determined by transfer characteristics of inverting amplifiers 9 and the input and output voltages of inverting amplifier 9 before short-circuited. Meanwhile, when switch SW1 is turned on, analog voltage Vin is applied from terminal 1 to node 5. Therefore, coupling capacitor 8 is charged by the difference voltage between voltages Vb and Vin.
Subsequently, when control signal .phi. is switched to the logical value "0", switches SW1 and SW3 are put in the OFF state while switch SW2 is put in the ON state. When switch SW3 is turned off, impedance at node 6, or input terminal of inverting amplifier 9 increases to infinity. Therefore, the charges stored at node 6 by coupling capacitor 8 for the period when control signal .phi. represents the logical value "1" are held until switch SW3 is put in the ON state again. Meanwhile, node 5 receives a predetermined voltage Vaj from terminal Tj instead of analog signal voltage Vin. Since the charges at node 6 are held, a voltage change (Vaj-Vin) appearing at node 5 is transmitted through coupling capacitor 8 to node 6 and inverted and amplified by inverting amplifier 9. Accordingly, when the amplification factor of inverting amplifier 9 is sufficiently large, the potential derived from output terminal 7 is Vdd (when Vin&gt;Vaj) corresponding to the "H" level or ground potential Vss (when Vin&lt;Vaj) corresponding to the "L" level. Thus, in the period where control signal .phi. represents the logical value "0", comparison is made between voltage Vin sampled during the period when control signal .phi. represents the logical value "1" and reference voltage Vaj output from reference voltage generating circuit RVG so as to output a binary signal corresponding to the comparison result.
As described above, the A/D converter comprising reference voltage generating circuit RVG constituted of two resistor networks compares voltages of (m.multidot.n-1) gradations obtained by dividing a difference voltage between reference voltage receiving terminals 2 and 3, with an analog voltage which is to be the digitized. As a result, output pattern of comparing portion CMPG has 2.sup.m.multidot.n-1 types. Encoder ENC outputs different binary data of N bit(s) (N is any natural number) corresponding to the respective 2.sup.m.multidot.n-1 output patterns. Therefore, in order to digitize an analog voltage received at analog voltage receiving terminal 1 with a resolution of N bit(s), values of m and n are selected such that the product (m.multidot.n) of the resistor number m in sub-resistor network SR and the resistor number n comprised in each of resistor networks RGl to Rgm constituting main resistor network MR becomes equal to 2.sup.N.
Meanwhile, before the reference voltage generating circuit constituted of two resistor networks has been proposed, the reference voltage generating circuits had been constituted of a single resistor network. That is, a reference voltage generating circuit was constituted of only main resistor network MR as shown in FIG. 9. In such a case, if reference voltage receiving terminals 2 and 3 are connected to ideal power sources having an output impedance of 0, output impedance Z(i, k) (i=1, 2, . . . , n; k=1, 2, . . . , m) of a given tap A(i, k) contained in main resistor network MR is shown as composite impedance of those resistor networks connected between tap A and reference voltage receiving terminal 3 (including series-connected x resistor elements of resistance value r, where x=n.multidot.(k-1)+i) and the other resistor networks connected between tap A and reference voltage receiving terminal 2 (including series-connected m.multidot.n-x resistor elements of resistance value r. Therefore, the above-mentioned output impedance Z(i, k) is given by the following expression. In the following expression, ".vertline..vertline." is the symbol for representing an operation ##EQU1##
FIG. 11 is a diagram showing the output impedance of reference voltage generating circuit RVG. In FIG. 11, the lateral direction represents the locations of taps in reference voltage generating circuit RVG (or location of corresponding output terminals Tj) in main resistor network MR and sub-resistor network SR, and the vertical direction represents the magnitude of impedances. FIG. 11 takes a case as an example that N=2, or the tap number of main resistor network MR is 3. In this case, according to the expression above, the impedances at output terminals T1 to T3 receiving three voltages derived from main resistor network MR, respectively, become larger as the corresponding taps get farther from reference voltage receiving terminals 2 and 3, and reach a maximum value at the center of main resistor network MR, as shown by the curve a. Thus, when reference voltage generating circuit RVG is constituted of main resistor network MR only, both impedances at reference voltage receiving terminals 2 and 3 are 0 if only they are connected to ideal power sources. However, impedances at those output terminals of reference voltage generating circuit RVG that correspond to the taps located in the center of main resistor network MR reach considerable values.
When the output terminals of reference voltage generating circuit RVG provide great impedances, the following problem will arise.
Turning back to comparator CMP in FIG. 10, in response to a switch of control signal .phi. in logical value from "1" to "0", the analogue voltage at node 5 which has been applied through analog voltage receiving terminal 1 changes to a voltage applied through terminal Tj from reference voltage generating circuit RVG. This causes coupling capacitor 8 to be discharged or charged at a speed inversely proportional to magnitude of the time constant obtained as product of the capacitance value of coupling capacitor 8 and the impedance of terminal Tj. When this discharging or charging has been completed, potential at node 5 settles at a level received at terminal Tj from reference voltage generating circuit RVG. Thus, since charges flow into or out of node 5 when the logical value of control signal .phi. is switched to "0", potential at terminal Tj fluctuates transitionally. Therefore, when the impedance at terminal Tj is great, it takes a long time for the reference voltage derived from terminal Tj to return to the initial value. This means that it takes a long time also for output of comparator CMP to settle at a correct logical value. In order to obtain correct data from encoder ENC, therefore, it is necessary to make the time sufficiently long in which control signal .phi. is held at the logical value "0" such that output of comparator CMP settles at the correct logical value. Accordingly, when the impedance of terminal Tj is large, the operation speed of the A/D converter is reduced.
In order to solve the problem above, it may be proposed to make the impedance at terminal Tj small. That is, main resistor network MR comprised in reference voltage generating circuit may be constituted of resistors having a small resistance value.
Now, the resistor elements in a monolithic IC are generally formed of an impurity-diffused layer, a polysilicon layer and the like to be of a rectangular configuration. If the resistance layer has the same depth, the resistance value of a resistor element is determined by the ratio between lengths of two sides of the rectangle. In order to form a resistor element with a small resistance value, the resistor layer is formed to have a long side vertical to a path of current and a short side parallel to the current path. That is, the resistor element with a small resistance value in a monolithic IC is laid out to have one long side and the other short side.
Meanwhile, practical patterns of the resistor elements formed on a monolithic IC deviate from an originally designed layout pattern approximately to the same degree irrespective of dimension of the designed layout pattern. Therefore, in order to restrict the ratio of the deviation to the designed layout pattern (relative error) as much as possible, in consideration of a dispersion of resistance values caused in manufacturing the resistor elements, the designed layout pattern must be made large. On the other hand, the layout pattern for a resistor element with a small resistance value must be a rectangle having one side substantially shorter than another side. As the shorter side has a smaller length, the relative error is increased. Therefore, in forming resistor elements with a small resistance value on a monolithic IC, a large layout pattern is required for the resistor elements. This means a reduction in the integration of the IC.
For the reason described above, when an A/D converter with a reference voltage generating circuit constituted of 2.sup.N resistor elements each having a low resistance value is incorporated in a one-chip LSI for example, each of the 2.sup.N resistor elements has to be formed to have a large layout pattern. If the resolution of this A/D converter is 8 bits for example, the reference voltage generating circuit RVG requires 2.sup.8 (=256) resistor elements, and if the resolution is 10 bits, the same requires 2.sup.10 (=1024) resistor elements. Thus, as a higher resolution is required of the A/D converter, a further reduction will be expected in the integration of LSI. Accordingly, it is difficult to reduce substantially resistance values of the resistor elements comprised in the reference voltage generating circuit.
Therefore, it has been proposed that reference voltage generating circuit RVG is constituted of main resistor network MR and sub-resistor network SR, as shown in FIG. 9. In order to obtain output of N bit(s) from an A/D converter, the reference voltage generating circuit shown in FIG. 9 is constituted of main resistor network MR with the number of constituent elements being 2.sup.N and of sub-resistor network SR with the number of constituent elements being 2.sup.N /n, which is much smaller than that of main resistor network MR. Therefore, when this reference voltage generating circuit RVG is formed on a monolithic IC, it becomes possible to form each resistor of sub-resistor network SR each in a large layout pattern. Accordingly, sub-resistor network SR constituted of resistor elements with sufficiently low resistance values can be formed on the LSI, without degrading accuracy of the elements.
Meanwhile, like main resistor network MR, sub-resistor network SR is also constituted of a series connection of a plurality of resistor elements having the same resistance value. Therefore, considering sub-resistor network SR only, output impedances of the taps contained therein become larger, as the corresponding tap gets apart farther from reference voltage receiving terminals 2 and 3, and reach a maximum value at the center of sub-resistor network SR. However, sub-resistor network SR can be constituted of resistor elements of a small resistance value. Therefore, the output impedance of sub-resistor network SR becomes small as a whole in comparison with that (curve a) of main resistor network MR not accompanied by any sub-resistor network SR, as indicated by the curve b in FIG. 11.
Each of the impedances at nodes A (1, n) to A (m-1, n) between sub-resistor network SR and main resistor network MR is considered as composite impedance of two resistor networks connected in the directions of sub-resistor network SR and main resistor network MR, respectively. That is, when impedances of the two resistor networks connected in the direction of sub-resistor network SR and main resistor network MR are represented as Z.sub.s and Z.sub.m, respectively, impedance Z at any node is shown by the following expression. ##EQU2##
Therefore, if composite impedance Z.sub.s of the resistor networks connected in the direction of sub-resistor network SR is substantially small relative to composite impedance Z.sub.M of the resistor networks connected in the direction of main resistor network MR (Z.sub.s /Z.sub.M .apprxeq.O), impedances at the respective nodes between main resistor network MR and sub-resistor network SR are equal to those at the corresponding taps in sub-resistor network SR. Further, impedances of those taps in main resistor network MR that are not connected to sub-resistor network SR represent a maximum value at the center of a resistor network (any of RGl to RGm) containing the tap. Therefore, the output impedance of the reference voltage generating circuit shown in FIG. 9 shows a curve based on the curve b, or curve c in FIG. 11. Accordingly, the output impedance of reference voltage generating circuit RVG is reduced as compared with the case the reference voltage generating circuit is constituted of main resistor network MR only (curve a).
As described above, when reference voltage generating circuit RVG is constituted of two resistor networks, the output impedance of reference voltage generating circuit RVG can be made small within a range applicable also to a monolithic IC.
Meanwhile, the resistance value r of the resistor elements constituting main resistor network MR and the resistance value R of the resistor elements constituting sub-resistor network SR are selected such that potentials obtained at the nodes between resistor networks RGl to Rgm by dividing a voltage between reference voltage receiving terminals 2 and 3 only in main resistor network MR become equal to those potentials obtained at the nodes between resistors Rl to Rm by dividing the voltage between reference voltage receiving terminals 2 and 3 only in sub-resistor network SR. Thus, no current flow is caused between main resistor network MR and sub-resistor network SR.
FIG. 12 is a schematic block diagram showing structure of a D/A converter.
Referring to FIG. 12, the D/A converter comprises digital signal input terminal 11 for receiving a digital signal to be converted into an analog voltage, analog voltage generating circuit 14 provided between reference voltage receiving terminals 12 and 13 to receive reference voltages of different magnitudes, decoder 15, voltage selecting portion 16, output buffer 17 and analog voltage output terminal 18. Analog voltage generating circuit 14 and reference voltage receiving terminals 12 and 13 correspond to reference voltage generating circuit RVG and reference voltage receiving terminals 2 and 3 in the D/A converter shown in FIG. 8, respectively.
Subsequently, operation of the A/D converter will be described. When a digital signal of N bit(s) is applied to digital signal input terminal 11, decoder 15 converts the digital signal of N bit(s) into a digital signal of 2.sup.N bits and outputs the converted signal. Meanwhile, analog voltage generating circuit 14 divides the difference voltage between the reference voltages applied to reference voltage receiving terminals 12 and 13 to apply 2.sup.N voltages of different magnitudes to voltage selecting portion 16. Voltage selecting portion 16 comprises 2.sup.N switches Sl to S (2.sup.N). Each of switches Sl to S(2.sup.N) is provided between one of the 2.sup.N outputs of analog voltage generating circuit 14 and an input terminal of output buffer 17. That is, as shown in the diagram, the 2.sup.N outputs of analog voltage generating circuit 14 correspond to switches Sl to S (2.sup.N) on a one-to-one basis. These switches Sl to S (2.sup.N) are turned on/off in response to output of decoder 15.
More specifically, switches Sl to S (2.sup.N) are turned on when either one of the binary voltages at the "L" and "H" levels, which correspond to the logical values "0" and "1", respectively, is received as a control voltage, and turned off when the other one is received as the control voltage. According to output of decoder 15, only one of the switches Sl to S (2.sup.N) is selectively turned on and all the other switches are turned off.
When decoder 15 converts the digital signal of N bit(s) into a digital signal which can turn on only one switch (any one of Sl to S(2.sup.N)) provided for analog voltages within the range indicated by the digital signal, the 2.sup.N outputs of decoder 15 are directly applied to switches SW1 to S(2.sup.N) as control voltages in a one-to-one correspondence. When decoder 15 does not make such conversion, the outputs of decoder 15 are further decoded by logical gates and the like in voltage selecting portion 16 to be converted into a digital signal which can turn on only one appropriate switch among switches Sl to S(2.sup.N). In this manner, voltage selecting portion 16 selectively applies one of the 2.sup.N analog voltages output from analog voltage generating circuit 14 to output buffer 17.
Output buffer 17 is a voltage follower-type operational amplifier having its non-inversion input terminal connected to its output terminal. Therefore, output buffer 17 buffers the analog voltage applied from voltage selecting portion 16 and then applies the same to analog voltage output terminal 18.
In this manner, an analog voltage indicated by the digital signal of N bit(s) is derived from analog voltage output terminal 18.
Meanwhile, when the digital signal applied to input terminal 11 is switched from one indicating an analog voltage within a certain range to another indicating an analog voltage within a different range, a switch that has not been in the on-state is turned on in voltage selecting portion 16. As a result, potential at the input terminal of output buffer 17 changes from one having been so far applied to another applied through the newly turned-on switch. At this time, a connection line between the input terminal of output buffer 17 and voltage selecting portion 16 is charged or discharged. A potential change at the input terminal of output buffer 17 caused by this charging or discharging is derived from output terminal 18 through output buffer 17. After the charging or discharging has been completed later, potential at the input terminal of output buffer 17 settles at the output potential of analog voltage generating circuit 14 that corresponds to the newly turned on switch. Following the above, potential at the output terminal of output buffer 17 also settles at an analog voltage corresponding to the input data signal of the present time. Accordingly, in order to convert a digital signal applied to input terminal 11 into a corresponding analog voltage as soon as possible and output the converted voltage to output terminal 18, potential at the input terminal of output buffer 17 should change desirably in a shortest possible time in response to a switch of the digital signal. That is, it is desirable for the input terminal of output buffer 17 to be charged or discharged in a shortest possible time. For that purpose, impedance at the input terminal of output buffer 17, or output impedance of analog voltage generating circuit 14 should be desirably low. Therefore, also in the D/A converter, a low output impedance is desirable for analog voltage generating circuit 14 corresponding to the above-mentioned reference voltage generating circuit. Thus, by employing the circuit shown in FIG. 9 as analog voltage generating circuit 14, operation speed of the D/A can be enhanced.
For the A/D and D/A converters of recent years used in audio equipments that require digital signal processings, those ones having a resolution no less than 10 bits (12 bits or 14 bits) have been put to practical use. However, since the operation frequency demanded of the A/D and D/A converters used in such audio equipments is no more than 1 MHz, the output impedance of a reference voltage generating circuit used therein needs not to be so low. However, for the A/D and D/A converters used in video equipments in which digital signal processings are necessary, a resolution of 8 bits and a very high operation frequency such as 20 Mhz are required, for example. Further, for the A/D and D/A converters used in the video equipments applied to high-definition broadcasting, a resolution of 10 bits and an operation frequency of 20 MHz or 50 MHz, or a resolution of 8 bits and an operation frequency no less than 50 Mhz are required. Thus, especially for those A/D and D/A converters used in video equipments, a substantially high operation speed as well as a high resolution are required. In these years, therefore, there has been need for A/D and D/A converters having a much higher operation speed than conventional ones and a high resolution. Accordingly, it has been required to reduce the output impedance of a reference voltage generating circuit used in those equipments. For this reason, such a reference voltage generating circuit as shown in FIG. 9 has been contrived.
However, such a conventional reference voltage generating circuit as shown in FIG. 9 comprises a sub-resistor network having a low impedance so as to reduce its output impedance. Therefore, impedances at the respective output terminals of the reference voltage generating circuit varies depending on the corresponding taps. That is, the output impedance of sub-resistor network SR which determines level of the output impedance of main resistor network MR becomes higher at a tap closer to the center of sub-resistor network SR. Therefore, impedances at the nodes (nodes between resistor networks RGl to RGm) between main resistor network MR and sub-resistor network SR become larger at a portion closer to the center of main resistor network MR. Meanwhile, impedances of those taps in the respective resistor networks GRl to GRm constituting main resistor network MR that are not connected to sub-resistor network SR become larger as the taps are located closer to the center of a corresponding resistor network, and not constant.
In the case of the A/D converter shown in FIG. 8, when the output impedances of reference voltage generating circuit RVG differ from one terminal to another, operable speeds of all comparator CMP do not represent the same value. Therefore, after the switch of control signal .phi. from logical value "1" to "0", if N outputs are fetched from comparing portion CMPG before the above-described transitional phenomenon ends in all comparators CMP, the respective accuracy of the logical values vary depending on the corresponding comparators CMP. As a result, the accuracy of output data of encoder ENC varies between bits. In order to avoid such a phenomenon, the operation frequency of the A/D converter must be determined according to the operable speed of the comparator CMP which is connected to one of the output terminals of reference voltage generating circuit RVG that has a maximum impedance. Thus, if output impedance of reference voltage generating circuit RVG differs from one terminal to another, the A/D converter is prevented from acquiring a high output accuracy and an enhanced operation frequency.
Similarly, in the case of D/A converters, if output impedance of analog voltage generating circuit 14 in FIG. 12 differs from one terminal to another, the time taken for potential at the input terminal of output buffer 17 to settle at a level corresponding to an input digital signal differs between digital signals. That is, according to the input digital signals, the operation speed of the D/A converter varies. Therefore, in order to improve the output accuracy of the D/A converter, timings to fetch an analog voltage from output terminal 18 need to be determined according to the time taken for a potential change caused at the output terminal of output buffer 17 when a switch in voltage selecting portion 16 is turned on that corresponds to the output terminal of analog voltage generating circuit 14 having a highest output impedance. Accordingly, if output impedance of analog voltage generating circuit 14 varies from one output terminal to another, the D/A converter is prevented from acquiring a high output accuracy and an enhanced operation frequency.
Further, in the reference voltage generating circuit for generating a plurality of linear voltages, main resistor network MR and sub-resistor network SR are each constituted of a plurality of resistor elements having the same resistance value. Generally, it is desirable for those linear analog circuits that various values indicative of circuit characteristics, such as impedance, do not represent any non-linear inconsistency.
As described above, if output impedance of a circuit used as a reference voltage generating circuit in an A/D converter or as an analog voltage generating circuit in a D/A converter differs from one terminal to another, functionality of the entire circuit including the circuit can not be enhanced.